Counters and Shift Registers: Ripple, Synchronous, Ring and Johnson

Once you can store a bit in a flip-flop, the next step is to connect several of them so that they count clock pulses or move data. Counters generate timing, divide frequencies and step through sequences. Shift registers convert between serial and parallel data, which is how a microcontroller drives dozens of LEDs from three pins. This tutorial covers asynchronous and synchronous counters, a complete mod-6 counter design using excitation tables and K-maps, and the main shift register configurations, including ring and Johnson counters.

Asynchronous (Ripple) Counters

In a ripple counter only the first flip-flop receives the external clock. Each flip-flop is set to toggle (T = 1, or J = K = 1), and its output clocks the next stage. With negative-edge-triggered flip-flops, each stage toggles when the previous output falls from 1 to 0, producing a binary up count. Each stage also divides its input frequency by 2, so an n-stage ripple counter divides the clock by 2^n.

3-bit ripple up counter, falling-edge triggered

Clock pulses : 1  2  3  4  5  6  7  8
Q0           : 1  0  1  0  1  0  1  0
Q1           : 0  1  1  0  0  1  1  0
Q2           : 0  0  0  1  1  1  1  0
Count Q2Q1Q0 : 1  2  3  4  5  6  7  0

Ripple counters are simple but slow, because the last stage changes only after the delays of all earlier stages add up. During that ripple time the outputs pass through false intermediate values. For example, going from 011 to 100 may briefly show 010 and 000. If those outputs drive a decoder, the decoder produces glitches.

Mod-N ripple counter by reset

To count from 0 to 9 (mod-10), detect the first unwanted state, 1010, with a NAND gate on Q3 and Q1, and connect its output to the active-low asynchronous clear of all flip-flops. The counter momentarily reaches 1010 and is immediately cleared to 0000. This works, but the brief invalid state is a known weakness. For a ready-made solution, the 74LS90 provides a decade counter in a single package.

Synchronous Counters

In a synchronous counter every flip-flop shares the same clock, so all outputs change together after one clock-to-Q delay. Logic in front of each flip-flop decides whether it should toggle. For a binary up counter built with T flip-flops, a bit toggles only when all lower bits are 1.

3-bit synchronous binary up counter with T flip-flops
T0 = 1
T1 = Q0
T2 = Q0 . Q1
(in general Tn = Q0 . Q1 ... Q(n-1))

Common synchronous counter ICs include the 74163, a 4-bit binary counter with synchronous clear and parallel load, and the 74161, which is similar but has an asynchronous clear. With a synchronous clear, a mod-N counter is built by detecting state N-1 instead of N, which avoids the glitch state completely.

Worked Design: Synchronous Mod-6 Counter with D Flip-Flops

The required sequence is 000, 001, 010, 011, 100, 101 and back to 000. States 110 and 111 are unused and treated as don't-cares. For a D flip-flop the excitation is simple: D must equal the desired next state.

Present Q2Q1Q0 | Next Q2Q1Q0 | D2 D1 D0
---------------+-------------+---------
     000       |     001     | 0  0  1
     001       |     010     | 0  1  0
     010       |     011     | 0  1  1
     011       |     100     | 1  0  0
     100       |     101     | 1  0  1
     101       |     000     | 0  0  0
     110       |     XXX     | X  X  X
     111       |     XXX     | X  X  X

Plot each D column on a 3-variable K-map and group, using the don't-cares at m6 and m7.

D0 = Q0'
D1 = Q1.Q0' + Q2'.Q1'.Q0
D2 = Q1.Q0  + Q2.Q0'

Lock-out check (unused states):
110 -> D2 = 0 + 1 = 1, D1 = 1 + 0 = 1, D0 = 1  -> 111
111 -> D2 = 1 + 0 = 1, D1 = 0 + 0 = 0, D0 = 0  -> 100 (valid)
The counter recovers to the main sequence within two clocks.

Always perform the lock-out check. If an unused state led only to other unused states, a power-on glitch could trap the counter forever. When that happens, assign specific next states to the unused codes instead of treating them as don't-cares.

Shift Registers

A shift register is a chain of D flip-flops where each Q feeds the next D. On every clock edge the stored pattern moves one position. Registers are classified by how data enters and leaves.

Type	Input	Output	Example IC and use
SISO	Serial	Serial	Digital delay line of n clocks
SIPO	Serial	Parallel	74HC595: drive 8 LEDs from 3 MCU pins, with an output latch
PISO	Parallel	Serial	74HC165: read 8 switches into an MCU over 3 pins
PIPO	Parallel	Parallel	Data holding register
Universal	Both	Both	74194: shift left, shift right, parallel load or hold

Ring and Johnson counters

Feeding the last output back to the first input makes a ring counter. Preloaded with 1000, a 4-bit ring cycles through 1000, 0100, 0010, 0001: four states from four flip-flops, each state decoded without any gates. Feeding back the complement of the last output makes a Johnson (twisted-ring) counter, which gives 2n states from n flip-flops. A 4-bit Johnson counter cycles 0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001, and each state can be decoded with a single 2-input gate. Only one bit changes per clock, so the decoded outputs are glitch-free.

Common Mistakes

Decoding ripple counter outputs directly and getting glitches. Use a synchronous counter or strobe the decoder.
Resetting a 74163 at state N instead of N-1. Its clear is synchronous and takes effect at the next edge.
Not initialising a ring counter. If it powers up as 0000 or 1111 it never leaves that state.
Skipping the lock-out check on counters with unused states.

Summary

Ripple counters chain toggling flip-flops and divide frequency by 2 per stage, but suffer accumulated delay. Synchronous counters clock every stage together and are designed with excitation tables and K-maps, as in the mod-6 example. Shift registers move data serially or in parallel; the 74HC595 and 74HC165 are everyday examples. Ring and Johnson counters are shift registers with feedback that give easily decoded sequences. All of these are special cases of finite state machines, the subject of the next tutorial.