CMOS Inverter Analysis and the VLSI Design Flow from RTL to GDSII

Almost every digital chip made today uses CMOS (complementary metal-oxide-semiconductor) logic, and the CMOS inverter is its simplest and most studied circuit. If you understand how two transistors form an inverter, how fast it switches and how much power it burns, you understand the core trade-offs of all digital VLSI. This tutorial analyses the inverter with worked calculations, shows how NAND and NOR gates extend the same idea, and then walks through the industrial design flow that turns Verilog into a manufactured chip.

How the CMOS Inverter Works

A PMOS transistor connects the output to VDD and an NMOS transistor connects the output to ground. Both gates are tied to the input. When the input is low, the PMOS is on and the NMOS is off, so the output is pulled to VDD. When the input is high, the NMOS is on and the PMOS is off, so the output is pulled to ground. In either steady state one transistor is off, so there is no DC path from supply to ground. This is why CMOS draws almost no static current, apart from leakage.

          VDD
           |
        |--+  PMOS (source at VDD)
 IN ----o|
        |--+
           +------ OUT
        |--+
 IN -----|    NMOS (source at GND)
        |--+
           |
          GND

Voltage transfer characteristic

Plotting Vout against Vin gives the voltage transfer characteristic (VTC). It has five regions: NMOS off and output at VDD; NMOS saturated and PMOS linear; both saturated, where the curve is steepest; NMOS linear and PMOS saturated; and PMOS off with output at 0 V. The steep middle region gives high gain, which is what restores degraded logic levels and makes CMOS noise margins large.

Switching Threshold and Transistor Sizing

The switching threshold VM is the input voltage at which Vin = Vout, with both transistors in saturation. Using the long-channel square-law model, it depends on the ratio of the transistor strengths k = μ Cox (W/L).

VM = ( Vtn + r (VDD - |Vtp|) ) / (1 + r),     r = sqrt(kp / kn)

Example: VDD = 1.8 V, Vtn = |Vtp| = 0.4 V

Case 1, kp = kn (r = 1):
VM = (0.4 + 1.4) / 2 = 0.9 V = VDD/2   (symmetric)

Case 2, equal widths, electron mobility about twice hole mobility (kp/kn = 0.5, r = 0.707):
VM = (0.4 + 0.707 x 1.4) / 1.707 = 0.81 V   (shifted low)

Because holes are less mobile than electrons, a PMOS of the same size is weaker. To get a symmetric threshold and equal rise and fall times, designers make the PMOS wider than the NMOS, typically two to three times, depending on the process. Short-channel effects in modern processes change the exact numbers, so real sizing is done with SPICE simulation using the foundry's models.

Delay and Power

Each switching event charges or discharges the load capacitance CL, made up of the next gates' input capacitance and wiring. Treating the on transistor as an equivalent resistance gives a first-order estimate of propagation delay. Power has a dynamic part from charging capacitance and a static part from leakage.

Propagation delay (RC estimate):  tp ≈ 0.69 Req CL
Example: Req = 10 kΩ, CL = 10 fF  ->  tp ≈ 0.69 x 1e4 x 1e-14 = 69 ps

Dynamic switching power:  P = α CL VDD^2 f
  α  = activity factor (fraction of clock cycles a node switches)
Example (whole block): α = 0.1, total C = 1 nF, VDD = 1.0 V, f = 1 GHz
  P = 0.1 x 1e-9 x 1.0 x 1e9 = 0.1 W

The VDD squared term explains why supply voltages have dropped across process generations and why techniques such as dynamic voltage and frequency scaling save so much power. Clock gating reduces α by stopping the clock to idle blocks. A small short-circuit current also flows during each transition while both transistors are briefly on, which is minimised by keeping input edges sharp.

Extending to NAND and NOR

A CMOS gate has a pull-down network of NMOS transistors and a dual pull-up network of PMOS transistors. Series in one network becomes parallel in the other.

Gate	NMOS pull-down	PMOS pull-up	Transistors
Inverter	One NMOS	One PMOS	2
2-input NAND	Two in series	Two in parallel	4
2-input NOR	Two in parallel	Two in series	4

NAND gates are usually preferred over NOR gates. In a NAND, the series transistors are the fast NMOS devices; in a NOR, the series stack is made of slow PMOS devices that must be made much wider to compensate. This is one reason standard-cell libraries and synthesis results lean heavily on NAND-based logic.

The Digital VLSI Design Flow

Specification: functions, interfaces, target clock frequency, power and area budget.
RTL design: describe the logic in Verilog, SystemVerilog or VHDL.
Functional verification: simulate with testbenches, often using UVM and coverage goals.
Logic synthesis: convert RTL into a gate-level netlist of standard cells from the foundry library, under timing constraints written in SDC format.
Design for test: insert scan chains so manufactured chips can be tested.
Floorplanning and power planning: place large blocks and I/O, and lay out power rails.
Placement: position every standard cell.
Clock tree synthesis: build a balanced clock network to minimise skew.
Routing: connect all cells with metal layers.
Sign-off: static timing analysis with extracted parasitics, design rule check (DRC), layout versus schematic (LVS), and power and IR-drop analysis.
Tape-out: deliver the final layout as a GDSII or OASIS file to the foundry.

Commercial flows use tools such as Synopsys Design Compiler and Cadence Genus for synthesis, Cadence Innovus or Synopsys IC Compiler II for place and route, and Synopsys PrimeTime for timing sign-off. Students can try the full flow for free with the open-source OpenLane flow, built on OpenROAD and Yosys, using the SkyWater SKY130 open process design kit. Analog and custom circuits follow a different path: schematic entry, SPICE simulation, hand-drawn layout, then the same DRC and LVS checks.

Common Mistakes and Summary

Sizing PMOS equal to NMOS and then wondering why rise time is slower than fall time.
Forgetting that dynamic power scales with VDD squared, not VDD.
Treating synthesis timing as final; real delays are known only after routing and extraction.
Skipping LVS, which is the only check that the layout actually matches the netlist.

The CMOS inverter uses complementary transistors so that one is always off, giving near-zero static power and full rail-to-rail outputs. Its switching threshold depends on the PMOS to NMOS strength ratio, its delay on equivalent resistance and load capacitance, and its dynamic power on α C VDD squared f. NAND and NOR follow from series-parallel duality. In industry, these cells are assembled automatically by the RTL-to-GDSII flow of synthesis, placement, clock tree, routing and sign-off.