Flip-Flops Explained: SR, JK, D and T with Excitation Tables
Combinational circuits forget their inputs as soon as they change. To build counters, registers, state machines and processors, a circuit must remember. The basic memory element is the latch or flip-flop, which stores one bit. This tutorial starts from the cross-coupled SR latch, explains the difference between level-sensitive latches and edge-triggered flip-flops, and then covers the SR, JK, D and T types with their characteristic equations and excitation tables. You will finish with timing parameters and a worked flip-flop conversion, the kind of question that appears in almost every university exam.
The SR Latch: Where Memory Begins
Connect two NOR gates so that each output feeds one input of the other gate. The feedback creates two stable states, Q = 1 or Q = 0, and the circuit stays in whichever state it was last put into. Input S (set) forces Q to 1, input R (reset) forces Q to 0, and with both inputs at 0 the latch holds its value.
NOR SR latch (active-high inputs) S R | Q(next) | Action ----+-----------+--------------------------- 0 0 | Q | Hold 0 1 | 0 | Reset 1 0 | 1 | Set 1 1 | invalid | Q = Q' = 0, unpredictable when released
A NAND-based latch works the same way but with active-low inputs, so S' = R' = 0 is the forbidden combination. The forbidden state is a real problem: if S and R return to 0 at the same moment, the latch settles into an unknown state. Adding an enable input gives a gated SR latch, and connecting R = S' gives a gated D latch, which eliminates the invalid case entirely.
Latch versus Edge-Triggered Flip-Flop
A gated latch is transparent while its enable is high: any change at D appears at Q during that whole interval. In a system where outputs feed back to inputs, this can let a signal race around the loop several times in one clock pulse. A flip-flop solves this by sampling its input only at a clock edge. Edge triggering is usually built as a master-slave pair of latches: the master is open while the clock is low, the slave is open while the clock is high, so the output can change only at the rising edge. Modern synchronous design uses edge-triggered flip-flops almost exclusively.
| Property | Latch | Edge-triggered flip-flop |
|---|---|---|
| Responds to | Level of enable | Rising or falling clock edge |
| Transparent period | Whole enable-high time | None, only an aperture around the edge |
| Typical IC | 74373 octal D latch | 7474 dual D, 74LS112 dual JK |
| Risk in feedback loops | Races and oscillation | Safe if timing is met |
The Four Flip-Flop Types
Each type is described by a characteristic table, which gives the next state Q+ from the inputs and present state, and a characteristic equation.
| Type | Characteristic equation | Behaviour | Typical use |
|---|---|---|---|
| SR | Q+ = S + R'Q, with SR = 0 | Set, reset, hold; S = R = 1 not allowed | Simple control flags |
| JK | Q+ = JQ' + K'Q | Like SR, but J = K = 1 toggles | Counters in older TTL designs |
| D | Q+ = D | Output copies D at the clock edge | Registers, pipelines, FPGAs |
| T | Q+ = T XOR Q | T = 1 toggles, T = 0 holds | Binary counters, frequency dividers |
The JK flip-flop fixes the forbidden state of SR by making J = K = 1 a toggle. In a level-triggered JK latch, however, a toggle with a long clock pulse causes the race-around condition: the output keeps toggling as long as the clock stays high. Master-slave or edge-triggered construction removes this. The D flip-flop is the simplest and is the one synthesis tools and FPGAs use; every other type can be made from a D flip-flop plus a little logic.
Excitation Tables and Flip-Flop Conversion
A characteristic table answers what the next state will be. An excitation table answers the reverse question: given a required transition, what inputs are needed? It is the key tool for designing counters and state machines. X means don't care.
Q -> Q+ | S R | J K | D | T --------+-------+-------+-----+---- 0 -> 0 | 0 X | 0 X | 0 | 0 0 -> 1 | 1 0 | 1 X | 1 | 1 1 -> 0 | 0 1 | X 1 | 0 | 1 1 -> 1 | X 0 | X 0 | 1 | 0
Worked example: build a T flip-flop from a JK flip-flop
Required: behave as T. List T, Q, Q+ and the JK inputs needed. T Q | Q+ | J K ----+----+----- 0 0 | 0 | 0 X 0 1 | 1 | X 0 1 0 | 1 | 1 X 1 1 | 0 | X 1 K-map for J: J = T K-map for K: K = T Connect J and K together and drive them with T.
The same method converts a D flip-flop into a T flip-flop. Since Q+ must equal T XOR Q and a D flip-flop gives Q+ = D, the required input is D = T XOR Q: one XOR gate between T and the D input, with Q fed back. To get a JK from a D flip-flop, set D = JQ' + K'Q.
Timing Parameters
- Setup time (tsu): the input must be stable this long before the active clock edge.
- Hold time (th): the input must remain stable this long after the edge.
- Clock-to-Q delay (tcq): time from the clock edge until the output changes.
- Asynchronous preset and clear: override the clock and force Q immediately; on the 7474 they are active low.
Maximum clock frequency of a path between two flip-flops Tclk(min) = tcq + tlogic(max) + tsu fmax = 1 / Tclk(min) Example: tcq = 2 ns, tlogic = 5 ns, tsu = 1 ns Tclk = 8 ns -> fmax = 125 MHz
If setup or hold is violated, the flip-flop can enter a metastable state, hovering between 0 and 1 for an unpredictable time. This is why signals from buttons or another clock domain are passed through two flip-flops in series, called a synchroniser, before use.
Summary
Feedback between two gates creates the SR latch, the simplest one-bit memory. Edge-triggered flip-flops sample only at a clock edge and avoid races. SR, JK, D and T differ in how their inputs set the next state, captured by their characteristic equations, while excitation tables tell you which inputs produce a required transition. Respect setup and hold times and synchronise asynchronous inputs. Next you will combine flip-flops into counters and shift registers.