PCB Clearance and Design Rules: Setting Up and Passing DRC in KiCad 8
Every fabrication house publishes a capability list: minimum track width, minimum gap, smallest drill, smallest annular ring and how close copper may come to the board edge. If your design breaks any of these, the fab either rejects it, charges more, or produces a board that fails intermittently. The Design Rules Checker (DRC) in KiCad compares your layout against rules you enter, so it is only as good as the rules you give it.
This article explains each important rule, shows where to set it in KiCad 8, adds net classes and a custom rule for high voltage, and walks through common DRC errors.
The Rules That Matter
| Rule | What it controls | Comfortable starting value |
|---|---|---|
| Minimum clearance | Gap between copper of different nets | 0.2 mm |
| Minimum track width | Narrowest copper track | 0.2 mm |
| Minimum annular width | Copper ring around a plated hole | 0.13 to 0.15 mm |
| Minimum via diameter | Via pad size | 0.6 mm |
| Minimum through hole | Smallest drill | 0.3 mm |
| Hole to hole clearance | Web of laminate between drills | 0.25 mm or more |
| Copper to edge clearance | Copper distance from Edge.Cuts | 0.3 to 0.5 mm |
| Silkscreen minimum text height | Legibility of printed text | about 0.8 to 1 mm |
These starting values are deliberately looser than what most low-cost fabs can make. Working above the minimum improves yield and lets you order from almost any fab without redesign. Always confirm the actual numbers on your chosen fab's capability page and tighten only where the design needs it, such as fine-pitch IC fan-out.
Entering Rules in Board Setup
- In the PCB Editor, open File > Board Setup.
- Under Design Rules > Constraints, enter the fab minimums: clearance, track width, annular width, via diameter, through-hole size, hole-to-hole and copper-to-edge clearance.
- Under Design Rules > Pre-defined Sizes, add the track widths and via sizes you plan to use, for example 0.25, 0.5 and 1.0 mm tracks. They then appear in the toolbar drop-down while routing.
- Under Design Rules > Net Classes, edit the Default class and add others such as
Power. - Under Design Rules > Violation Severity, leave most items as errors. Downgrade only items you understand, such as silkscreen overlap on a prototype.
Rules saved in Board Setup live in the .kicad_pro file, and you can import them into another project with the Import Settings from Another Board button at the bottom of the dialog. Many fabs and community users publish ready-made KiCad rule sets.
Net Classes and Custom Rules
Net classes group nets that share width and clearance needs. A typical small board needs only three.
| Net class | Track width | Clearance | Example nets |
|---|---|---|---|
| Default | 0.25 mm | 0.2 mm | GPIO, I2C, SPI |
| Power | 0.8 mm | 0.25 mm | VIN, +5V, motor supply |
| USB | Set by impedance | 0.2 mm | USB_D+, USB_D- |
Assign nets to classes in the Net Classes page using patterns such as +5V or /MOTOR*. For rules that classes cannot express, use Design Rules > Custom Rules. The language is simple. This example demands 2 mm clearance between a high-voltage class and everything else, and requires a wider annular ring for vias on power nets.
(version 1)
# Keep high voltage copper 2 mm away from all other nets
(rule "HV clearance"
(condition "A.NetClass == 'HV' && B.NetClass != 'HV'")
(constraint clearance (min 2mm)))
# Power vias need a generous annular ring
(rule "Power via ring"
(condition "A.Type == 'Via' && A.NetClass == 'Power'")
(constraint annular_width (min 0.2mm)))Click Check Rule Syntax at the bottom of the Custom Rules page after editing, so that a typing mistake is caught now rather than discovered after the boards arrive.
Running DRC and Fixing Errors
Open Inspect > Design Rules Checker and click Run DRC. Keep Refill all zones before performing DRC and Test for parity between PCB and schematic switched on. Results appear in tabs for violations, unconnected items, schematic parity and ignored tests. Clicking an entry zooms to it on the board.
| Error | Typical fix |
|---|---|
| Clearance violation | Move the track, use a narrower width, or reroute around the pad |
| Track width less than minimum | Track drawn with a too-small width; select it and change width with E |
| Annular width too small | Increase via pad size or reduce drill |
| Courtyards overlap | Parts too close; move them apart |
| Board edge clearance violation | Pull copper or zones back from Edge.Cuts |
| Unconnected items | Route the missing connection or refill zones |
| Missing footprint or extra footprint | Board and schematic differ; run Update PCB from Schematic |
Common Mistakes
- Running DRC with default rules that do not match the fab, then trusting a clean result.
- Excluding errors in bulk to make the list empty. Each exclusion should be a deliberate, documented decision.
- Not refilling zones before DRC, so stale copper pours hide or create violations.
- Forgetting that rules use the board units; type
mmexplicitly in custom rules to avoid confusion.
Summary
Design rules translate your fab's capabilities and your circuit's safety needs into numbers KiCad can check. Enter constraints and pre-defined sizes in Board Setup, group nets into classes, use custom rules for special cases, and run DRC with zone refill and schematic parity enabled. A board that passes DRC against realistic rules is ready for fabrication output.