555 Timer in Astable and Monostable Modes With Worked Calculations

The 555 timer has been in production since the early 1970s and is still one of the most used ICs in student labs. With a couple of resistors and a capacitor it produces a continuous square wave (astable mode) or a single timed pulse when triggered (monostable mode). This tutorial explains what happens inside the chip, why the timing formulas look the way they do, and how to calculate component values for both modes.

Pinout and Internal Operation

Pin	Name	Function
1	GND	Ground
2	TRIG	Starts timing when pulled below 1/3 Vcc; output goes high
3	OUT	Output, can source or sink up to about 200 mA on the bipolar NE555
4	RESET	Active low; tie to Vcc when not used
5	CTRL	Access to the 2/3 Vcc reference; decouple with 10 nF to ground
6	THR	Ends timing when it rises above 2/3 Vcc; output goes low
7	DIS	Open-collector discharge transistor, shorted to ground while output is low
8	VCC	Supply, 4.5 V to 16 V for the NE555

Inside are three equal resistors forming a divider that creates reference voltages at 1/3 and 2/3 of Vcc, two comparators, a flip-flop, an output stage and the discharge transistor. The timing capacitor charges through external resistors. When its voltage reaches 2/3 Vcc, the threshold comparator resets the flip-flop: the output goes low and the discharge transistor turns on. When the trigger input falls below 1/3 Vcc, the flip-flop is set: output high, discharge off.

Because the thresholds are fixed fractions of Vcc, the timing is largely independent of the supply voltage. The factors 0.693 and 1.1 in the formulas come from the exponential RC charging curve: ln(2) = 0.693 for charging from 1/3 to 2/3 Vcc, and ln(3) = 1.0986 for charging from 0 to 2/3 Vcc.

Astable Mode

Vcc --+--------------+----- pin 8, pin 4
      |
     [R1]
      |
      +------------------ pin 7 (DIS)
      |
     [R2]
      |
      +------------------ pin 6 (THR) and pin 2 (TRIG)
      |
     [C]
      |
GND --+------------------ pin 1      pin 5 -> 10 nF -> GND

High time:   tH = 0.693 x (R1 + R2) x C
Low time:    tL = 0.693 x R2 x C
Period:      T  = 0.693 x (R1 + 2 x R2) x C
Frequency:   f  = 1.44 / ((R1 + 2 x R2) x C)
Duty cycle:  D  = (R1 + R2) / (R1 + 2 x R2)

The capacitor charges through R1 and R2 and discharges through R2 alone into pin 7, so the output oscillates between charging (output high) and discharging (output low) with the capacitor swinging between 1/3 and 2/3 Vcc. Since the high time includes R1, the duty cycle in this basic circuit is always above 50%.

Worked example: LED flasher

R1 = 1 kΩ, R2 = 10 kΩ, C = 10 µF.

tH = 0.693 x 11 000 x 10e-6 = 76.2 ms
tL = 0.693 x 10 000 x 10e-6 = 69.3 ms
T  = 145.5 ms
f  = 1 / 0.1455 = 6.87 Hz
D  = 11 / 21 = 52.4%

Worked example: designing for 1 kHz

Choose C = 10 nF and aim for a duty cycle near 50%, so make R1 small relative to R2. Taking R1 = 1 kΩ, solve for R2:

R1 + 2 x R2 = 1.44 / (f x C) = 1.44 / (1000 x 10e-9) = 144 kΩ
2 x R2 = 144 - 1 = 143 kΩ  ->  R2 = 71.5 kΩ  -> use 68 kΩ
Check: f = 1.44 / ((1k + 136k) x 10 nF) = 1051 Hz
D = 69 / 137 = 50.4%

For a duty cycle below 50%, add a diode across R2 (anode at pin 7) so the capacitor charges through R1 and the diode only; then tH depends on R1 and tL on R2, allowing any ratio.

Monostable Mode

In monostable mode, pins 6 and 7 are joined and connected to the capacitor and to Vcc through a single resistor R. The trigger pin is held high by a pull-up and briefly pulled low by a push button or a signal. The output then goes high for a fixed time while C charges from near 0 V to 2/3 Vcc, after which the discharge transistor empties the capacitor and the output returns low.

Pulse width:  T = 1.1 x R x C

Example: R = 100 kΩ, C = 100 µF
T = 1.1 x 100 000 x 100e-6 = 11 s

Example: R = 47 kΩ, C = 10 µF
T = 1.1 x 47 000 x 10e-6 = 0.517 s

Uses include a timed staircase light, a switch debouncer that outputs one clean pulse per press, and a missing-pulse detector. The trigger pulse must be shorter than the output pulse; if the trigger is held low longer, the output stays high until it is released.

To check a monostable design quickly, rearrange the formula for the component you need. For a 5 s staircase-light delay with a 47 µF capacitor, R = T / (1.1 x C) = 5 / (1.1 x 47e-6) = 96.7 kΩ, so a 100 kΩ resistor gives about 5.2 s. If you need an adjustable delay, use a fixed resistor of about 10 kΩ in series with a 1 MΩ potentiometer; the fixed part keeps the timing resistance from ever reaching zero, which would leave pins 6 and 7 connected directly to Vcc and overload the discharge transistor when it turns on.

Design Tips and Troubleshooting

Keep timing resistors between about 1 kΩ and 1 MΩ. Very low values overload the discharge transistor; very high values make leakage current matter.
Electrolytic capacitors have wide tolerance and leakage, so long delays will differ from calculation; use film capacitors for accurate timing.
Always decouple Vcc with 100 nF plus a larger electrolytic; the bipolar NE555 draws a current spike at every output transition.
Tie RESET (pin 4) to Vcc. A floating reset causes random stopping.
The CMOS versions (such as the TLC555 and ICM7555) work from lower voltages and draw far less current, but cannot drive heavy loads directly.
Driving a relay from pin 3: add a flyback diode across the coil.

Summary

The 555 compares a capacitor voltage against 1/3 and 2/3 of Vcc. In astable mode, f = 1.44 / ((R1 + 2R2)C) with a duty cycle of (R1 + R2) / (R1 + 2R2); in monostable mode the pulse lasts 1.1RC. Choose reasonable resistor values, accurate capacitors for precise timing, and decouple the supply well, and the 555 will do exactly what the formulas predict.