CAN Bus Basics: Differential Signalling, Frames and Arbitration
Controller Area Network (CAN) was developed by Bosch for cars, where dozens of electronic control units must share data reliably in an electrically noisy environment. Today it also runs in tractors, industrial machines, e-bikes, medical equipment and robots. CAN uses a single twisted pair, lets any node transmit when the bus is free, and resolves collisions without losing the winning message.
This article explains the physical layer, the classical CAN data frame field by field, how arbitration works, how errors are handled, and how to calculate frame time and bus load.
Physical Layer: Dominant, Recessive and Termination
CAN uses two wires, CANH and CANL, as a differential pair. A transceiver chip such as the TJA1050, MCP2551 or SN65HVD230 converts the controller's TX and RX logic signals to bus voltages.
| State | Logic value | CANH (typical) | CANL (typical) | Differential |
|---|---|---|---|---|
| Recessive | 1 | About 2.5 V | About 2.5 V | About 0 V |
| Dominant | 0 | About 3.5 V | About 1.5 V | About 2 V |
Dominant always overrides recessive: if one node drives dominant while others send recessive, the bus is dominant. This wired-AND behaviour is what makes arbitration possible. Because receivers look at the difference between CANH and CANL, noise that hits both wires equally cancels out.
The bus must be terminated with a 120 ohm resistor at each physical end, matching the cable's characteristic impedance and stopping reflections. With power off, measuring between CANH and CANL should read about 60 ohms, the two resistors in parallel. A reading of 120 ohms means one terminator is missing; around 40 ohms means there is one too many.
| Bit rate | Approximate maximum bus length |
|---|---|
| 1 Mbit/s | About 40 m |
| 500 kbit/s | About 100 m |
| 250 kbit/s | About 250 m |
| 125 kbit/s | About 500 m |
Length is limited because every node must see each bit, including the round trip during arbitration, within one bit time. These are commonly quoted guide values; transceiver and cable delays decide the exact figure.
The Classical CAN Data Frame
| SOF | Identifier | RTR | IDE | r0 | DLC | Data | CRC | CRC | ACK | ACK | EOF | IFS | | | (11 bits) | | | |(4) | (0-64) |(15) | del | slot| del | (7) | (3) | 1 11 1 1 1 4 0-64 15 1 1 1 7 3
| Field | Bits | Purpose |
|---|---|---|
| SOF | 1 | Dominant start-of-frame bit; synchronises all nodes |
| Identifier | 11 (standard) or 29 (extended) | Message ID and priority; lower value means higher priority |
| RTR | 1 | Dominant for data frame, recessive for remote request |
| IDE | 1 | Dominant for standard 11-bit ID, recessive for extended |
| DLC | 4 | Data length code, 0 to 8 bytes |
| Data | 0 to 64 | The payload |
| CRC | 15 + delimiter | Error detection over the frame |
| ACK | Slot + delimiter | Any node that received correctly drives the slot dominant |
| EOF | 7 | Seven recessive bits end the frame |
Notice that CAN frames carry an identifier for the message, not a destination address. Every node receives every frame and uses acceptance filters to keep the IDs it cares about.
Bitwise Arbitration
When two nodes start transmitting at the same time, each one reads the bus back while sending its identifier. A node that sends recessive (1) but reads dominant (0) knows another node has a lower ID, stops transmitting, and becomes a receiver. The node with the lowest ID never notices the contest and its frame goes through intact.
Node A ID 0x65 = 000 0110 0101 Node B ID 0x6A = 000 0110 1010 Bit: 10 9 8 7 6 5 4 3 2 1 0 Node A: 0 0 0 0 1 1 0 0 1 0 1 Node B: 0 0 0 0 1 1 0 1 ... <- sends 1, sees 0, backs off at bit 3 Bus: 0 0 0 0 1 1 0 0 1 0 1 <- Node A wins (0x65 < 0x6A)
This is non-destructive arbitration: no time is wasted on collisions, and message priority is fixed by the ID chosen during system design.
Bit Stuffing and Error Handling
Receivers resynchronise their clocks on edges. To guarantee edges, after five identical consecutive bits the transmitter inserts one bit of the opposite value, which the receiver removes. Stuffing applies from SOF to the end of the CRC field. Six identical bits in that region is therefore a stuff error.
CAN detects bit, stuff, CRC, form and acknowledgement errors. A node that detects one sends an error frame, and the transmitter retries automatically. Each node keeps transmit and receive error counters (TEC and REC). Above 127 the node becomes error passive and signals errors more quietly; if TEC exceeds 255 it goes bus off and stops transmitting, so a faulty node cannot jam the network.
Worked Example: Frame Time and Bus Load
Standard data frame with 8 data bytes, before stuffing:
SOF 1 + ID 11 + RTR 1 + IDE 1 + r0 1 + DLC 4 = 19
+ Data 64 + CRC 15 + CRC del 1 + ACK 2 + EOF 7 = 108 bits
+ IFS 3 = 111 bits
Worst-case stuff bits: 24 -> 135 bits
At 500 kbit/s, bit time = 2 us
Frame time = 111 x 2 = 222 us (no stuffing)
= 135 x 2 = 270 us (worst case)
Bus load for 10 such messages every 10 ms:
10 x 270 us / 10 ms = 27 %Designers usually keep bus load well below 100 percent, often under about 50 to 70 percent, so that high-priority messages are not delayed by long queues and retransmissions.
Hobby Hardware and Common Mistakes
Many STM32 and ESP32 chips include a CAN controller and need only a transceiver. For Arduino Uno, the common module pairs an MCP2515 SPI CAN controller with a TJA1050 transceiver; check the crystal on your module, often 8 MHz, because the library's bit-timing settings depend on it. CAN FD extends the payload to 64 bytes and allows a faster data phase, but classical CAN controllers like the MCP2515 do not support it.
- Missing or extra 120 ohm terminators; measure 60 ohms with power off.
- Mismatched bit rates or wrong crystal setting; no frames are acknowledged.
- A single node on the bus: with nobody to acknowledge, it reports ACK errors and keeps retrying.
- Long stubs from the main bus to each node, which cause reflections at higher bit rates.
- Forgetting a common ground reference between nodes powered from different supplies.
Summary
CAN is a differential, multi-master bus with dominant 0 and recessive 1, terminated by 120 ohms at both ends. Frames carry an identifier that doubles as priority, and bitwise arbitration lets the lowest ID win without losing time. Bit stuffing, CRC, acknowledgement and error counters make the bus robust. An 8-byte standard frame is 111 bits plus up to 24 stuff bits, which lets you calculate frame time and bus load before you build.